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cy7c006a/cy7c007a cy7c016a/cy7c017a 32 k/16 k 8, 16 k 9 dual-port static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-06045 rev. *f revised december 17, 2010 32 k/16 k 8, 16 k 9 dual-port static ram features true dual-ported memory cells which allow simultaneous access of the same memory location 16 k 8 organization (cy7c006a) 32 k 8 organization (cy7c007a) 16 k 9 organization (cy7c016a) 32 k 9 organization (cy7c017a) 0.35-micron cmos for optimum speed/power high-speed access: 12 [1] /15/20 ns low operating power ? active: i cc = 180 ma (typical) ? standby: i sb3 = 0.05 ma (typical) fully asynchronous operation automatic power-down expandable data bus to 16/18 bits or more using master/slave chip select when using more than one device on-chip arbitration logic semaphores included to permit software handshaking between ports int flags for port-to-port communication pin select for master or slave commercial temperature range available in 68-pin plcc (cy7c006a, cy7c007a and cy7c017a), 64-pin tqfp (cy7 c006a), and in 80-pin tqfp (cy7c007a and cy7c016a) pb-free packages available i/o control address decode a 0l ?a 13/14l ce l oe l r/w l busy l i/o control interrupt semaphore arbitration sem l int l m/s logic block diagram a 0l ?a 13/14l true dual-ported ram array a 0r ?a 13/14r ce r oe r r/w r busy r sem r int r address decode a 0r ?a 13/14r [2] [2] [3] [3] r/w l oe l i/o 0l ?i/o 7/8l ce l r/w r oe r i/o 0r ?i/o 7/8r ce r 14/15 8/9 14/15 8/9 14/15 14/15 [4] [4] [4] [4] notes 1. see page 7 for load conditions. 2. i/o 0 ?i/o 7 for x8 devices; i/o 0 ?i/o 8 for x9 devices. 3. busy is an output in master mode and an input in slave mode. 4. a 0 ?a 13 for 16k; a 0 ?a 14 for 32k devices. cy7c007a32 k/16 k 8, 16 k 9 dual-port static ram [+] feedback
cy7c006a/cy7c007a cy7c016a/cy7c017a document number: 38-06045 rev. *f page 2 of 22 contents pin configurations ........................................................... 3 selection guide ................................................................ 4 pin definitions .................................................................. 5 architecture ...................................................................... 5 functional description ..................................................... 5 write operation ........................................................... 5 read operation ........................................................... 5 interrupts ..................................................................... 5 busy ............................................................................ 6 master/slave ............................................................... 6 semaphore operation ............ .............. .............. ......... 6 maximum ratings ............................................................. 7 operating range ............................................................... 7 electrical characteristics ................................................. 7 capacitance table ............................................................ 8 ac test loads and waveforms ....................................... 8 ac test loads (applicable to ?12 only) ......................... 8 switching characteristics ................................................ 9 data retention mode ...................................................... 10 timing .............................................................................. 10 switching waveforms .................................................... 11 read cycle no. 1 (either port address access) ....... 11 read cycle no. 2 (either port ce /oe access) ......... 11 read cycle no. 3 (either port ) ................. ............ ..... 11 write cycle no. 1: r/w controlled timing ................ 12 write cycle no. 2: ce controlled timing .................. 12 semaphore read after write timing, either side ..... 13 timing diagram of semaphor e contention ............... 13 timing diagram of read with busy (m/s =high) .... 14 write timing with busy input (m/s =low) ................. 14 ce l valid first: ........................................................... 15 left address valid first: ............................................ 15 busy timing diagram no. 1 (ce arbitration) ............. 15 busy timing diagram no. 2 (address arbitration) .... 15 interrupt timing diagrams ......................................... 16 ordering information ...................................................... 18 16k x 8 asynchronous dual-p ort sram ................... 18 ordering code definitions ..... .................................... 18 package diagrams .......................................................... 19 document history page ................................................. 21 sales, solutions, and legal information ...................... 22 worldwide sales and design s upport ......... .............. 22 products .................................................................... 22 psoc solutions ......................................................... 22 [+] feedback
cy7c006a/cy7c007a cy7c016a/cy7c017a document number: 38-06045 rev. *f page 3 of 22 pin configurations notes 5. this pin is i/o for cy7c017a only. 6. a 14 is a no connect pin for 16k devices. top view 68-pin plcc v cc oe l i/o 1l i/o 0l a 12l a 11l a 10l a 9l a 8l a 7l a 6l a 13l ce l sem l r/w l i/o 2l i/o 3l i/o 4l i/o 5l i/o 6l i/o 7l v cc gnd i/o 0r i/o 1r i/o 2r i/o 3r i/o 4r i/o 5r gnd v cc a 4l a 3l a 2l a 1l a 0l gnd busy l busy r m/s a 0r a 1r a 2r a 3r a 4r int l int r gnd oe r i/o 7r a 5r a 12r a 11r a 10r a 9r a 8r a 7r a 6r a 13r ce r sem r r/w r a 5l nc(i/o 8l ) i/o6 r cy7c007a (32k x 8) 24 25 26 10 11 12 13 14 15 48 47 46 45 44 40 41 27 42 28 43 29 30 31 32 33 68 34 67 35 66 36 65 37 64 38 63 39 62 61 16 59 58 57 56 55 54 53 52 51 50 49 60 9 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 nc(i/o 8r ) [5] [5] a 14r a 14l cy7c017a (32k x 9) cy7c006a (16k x 8) [ 6 ] [6] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 37 36 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 44 45 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 64 65 63 62 61 80-pin tqfp top view i/o 2l i/o 3l i/o 4l i/o 5l i/o 6l i/o 7l v cc gnd i/o 0r i/o 1r 2r i/o 3r i/o 4r 5r gnd v cc v cc oe l i/o 0l a 5l a 12l a 11l a 10l a 9l a 8l a 7l a 6l ce l sem l r/w l a 4l a 3l a 2l a 1l a 0l gnd busy l m/s a 0r a 1r a 2r a 3r a 4r int l gnd oe r i/o 6r a 12r a 11r a 10r a 9r a 8r a 7r a 6r ce r sem r r/w r cy7c007a (32k x 8) busy r int r nc a nc nc nc nc nc nc nc nc nc a 5r i/o 7r nc i/o i/o nc i/o 1l 13r a 13l a 14l a 14r nc nc cy7c016a (16k x 9) [6] [6] [+] feedback
cy7c006a/cy7c007a cy7c016a/cy7c017a document number: 38-06045 rev. *f page 4 of 22 pin configurations (continued) 64-pin tqfp top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 50 32 49 16 gnd oe r i/o 2l i/o 3l i/o 4l i/o 5l i/o 6l i/o 7l v cc gnd i/o 0r i/o 1r i/o 2r i/o 3r i/o 4r i/o 5r i/o 6r gnd v cc a 4l a 3l a 2l a 1l a 0l gnd busy l busy r m/s a 0r a 1r a 2r a 3r a 4r int l int r i/o 7r a 5r a 12r a 11r a 10r a 9r a 8r a 7r a 6r a 13r ce r sem r r/w r v cc oe l i/o 1l i/o 0l a 5l a 12l a 11l a 10l a 9l a 8l a 7l a 6l a 13l ce l sem l r/w l cy7c006a (16k x 8) selection guide cy7c006a cy7c007a cy7c016a cy7c017a ?12 [7] cy7c006a cy7c007a cy7c016a cy7c017a ?15 cy7c006a cy7c007a cy7c016a cy7c017a ?20 maximum access time (ns) 12 15 20 typical operating current (ma) 195 190 180 typical standby current for i sb1 (ma) (both ports ttl level) 55 50 45 typical standby current for i sb3 (ma) (both ports cmos level) 0.05 0.05 0.05 note 7. see page 7 for load conditions. [+] feedback
cy7c006a/cy7c007a cy7c016a/cy7c017a document number: 38-06045 rev. *f page 5 of 22 architecture the cy7c006a, cy7c007a, cy7c016a and cy7c017a consist of an array of 32k/16k words of 8 bits and 32k words of 9 bits each of dual-port ram cells, i/o and address lines, and control signals (ce , oe , r/w ). these control pins permit independent access for reads or writes to any location in memory. to handle simultaneous writes/reads to the same location, a busy pin is provided on each port. two interrupt (int ) pins can be utilized for port-to-port communication. two semaphore (sem ) control pins are used for allocating shared resources. with the m/s pin, the devices can function as a master (busy pins are outputs) or as a slave (busy pins are inputs). the devices also have an automatic power-down feature controlled by ce . each port is provided with its own output enable control (oe ), which allows data to be read from the device. functional description the cy7c006a, cy7c007a, cy7c016a, and cy7c017a are low-power cmos 32k 8/9 and 16k 8/9 dual-port static rams. various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. the devices can be utilized as standalone 8/9-bit dual-port static rams or multiple devices can be combined in order to function as a 16/18-bit or wider master/slave dual-port static ram. an m/s pin is provided for implementing 16/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. application area s include interp rocessor/multi- processor designs, communications status buffering, and dual-port video/graphics memory. each port has independent control pins: chip enable (ce ), read or write enable (r/w ), and output enable (oe ). two flags are provided on each port (busy and int ). busy signals that the port is trying to access the same location currently being accessed by the other port. the interrupt flag (int ) permits communication between ports or systems by means of a mail box. the semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. the semaphore logic is comprised of eight shared latches. only one side can control the latch (semaphore) at any time. cont rol of a semaphore indicates that a shared resource is in use. an automatic power-down feature is controlled independent ly on each port by a chip select (ce ) pin. the cy7c006a, cy7c007a and cy7c017a are available in 68-pin plcc packages, the cy7c006a is also available in 64-pin tqfp, and the cy7c007a and cy7c016a are also available in 80-pin tqfp packages. write operation data must be set up for a duration of t sd before the rising edge of r/w in order to guarantee a valid write. a write operation is controlled by either the r/w pin (see write cycle no. 1 waveform) or the ce pin (see write cycle no. 2 waveform). required inputs for non-contention operations are summa- rized in table 1 . if a location is being written to by one port and the opposite port attempts to read that loca tion, a port-to-port flowthrough delay must occur before the data is read on the output; otherwise the data read is not deterministic. data will be valid on the port t ddd after the data is presented on the other port. read operation when reading the device, the user must assert both the oe and ce pins. data will be available t ace after ce or t doe after oe is asserted. if the user wishes to access a semaphore flag, then the sem pin must be asserted instead of the ce pin, and oe must also be asserted. interrupts the upper two memory locations may be used for message passing. the highest memory lo cation (7fff) is the mailbox for the right port and the second-highest memory location pin definitions left port right port description ce l ce r chip enable r/w l r/w r read/write enable oe l oe r output enable a 0l ?a 14l a 0r ?a 14r address i/o 0l ?i/o 8l i/o 0r ?i/o 8r data bus input/output (i/o 0 ?i/o 7 for 8 devices and i/o 0 ?i/o 8 for 9) sem l sem r semaphore enable int l int r interrupt flag busy l busy r busy flag m/s master or slave select v cc power gnd ground nc no connect [+] feedback
cy7c006a/cy7c007a cy7c016a/cy7c017a document number: 38-06045 rev. *f page 6 of 22 (7ffe) is the mailbox for the left port. when one port writes to the other port?s mailbox, an interrupt is generated to the owner. the interrupt is reset when the owner reads the contents of the mailbox. the message is user defined. each port can read the other po rt?s mailbox without resetting the interrupt. the active state of th e busy signal (to a port) prevents the port from setting the interrupt to the winning port. also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. if an application does not require message passing, do not connect the interrupt pin to the processor?s interrupt request input pin. the operation of the interrupts and their interaction with busy are summarized in table 2 . busy the cy7c006a, cy7c007a, cy7c016a and cy7c017a provide on-chip arbitration to resolve simultaneous memory location access (contention). if both ports? ce s are asserted and an address match occurs within t ps of each other, the busy logic will determine which port has access. if t ps is violated, one port will definitely gain permission to the location, but it is not predictable which port will get that permission. busy will be asserted t bla after an address match or t blc after ce is taken low. master/slave a m/s pin is provided in order to expand the word width by config- uring the device as either a master or a slave. the busy output of the master is connected to the busy input of the slave. this will allow the device to interface to a master device with no external components. writing to slave devices must be delayed until after the busy input has settled (t blc or t bla ), otherwise, the slave chip may begin a write cycle during a contention situation. when tied high, the m/s pin allows the device to be used as a master and, therefore, the busy line is an output. busy can then be used to send the arbitration outcome to a slave. semaphore operation the cy7c006a, cy7c007a, cy7c016a and cy7c017a provide eight semaphore latches, which are separate from the dual-port memory locations. semaphores are used to reserve resources that are shared between the two ports. the state of the semaphore indicates that a resource is in use. for example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. the left port then verifies its success in setting the latch by reading it. after writing to the semaphore, sem or oe must be deasserted for t sop before attempting to read the semaphore. the semaphore value will be available t swrd + t doe after the rising edge of the semaphore write. if the left port was successful (reads a zero), it assumes control of the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore. when the right side has relinquished control of the semaphore (by writing a one), the left side will succeed in gaining control of the semaphore. if the left side no longer requires the semaphore, a one is written to cancel its request. semaphores are accessed by asserting sem low. the sem pin functions as a chip select for the semaphore latches (ce must remain high during sem low). a 0?2 represents the semaphore address. oe and r/w are used in the same manner as a normal memory access. when writing or reading a semaphore, the other addre ss pins have no effect. when writing to the semaphore, only i/o 0 is used. if a zero is written to the left port of an available semaphore, a one will appear at the same semaphore address on the right port. that semaphore can now only be modified by the side showing zero (the left port in this case). if the left port now relinquishes control by writing a one to the semaphore, the semaphore will be set to one for both sides. however, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. table 3 shows sample semaphore opera- tions. when reading a semaphore, all data lines output the semaphore value. the read value is latched in an output register to prevent the semaphore from changing stat e during a write from the other port. if both ports attempt to access the semaphore within t sps of each other, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore. [+] feedback
cy7c006a/cy7c007a cy7c016a/cy7c017a document number: 38-06045 rev. *f page 7 of 22 maximum ratings [8] exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature ................................. ?65 ? c to +150 ? c ambient temperature with power applied ............................................ ?55 ? c to +125 ? c supply voltage to ground potentia l................?0.3v to +7.0v dc voltage applied to outputs in high z state ................................................?0.5v to +7.0v dc input voltage [10] ........................................?0.5v to +7.0v output current into outputs (low)............................. 20 ma static discharge voltage....... ........... ............ .............. >2001v latch-up current ..................................................... >200 ma operating range range ambient temperature v cc commercial 0 ? c to +70 ? c 5v ? 10% electrical characteristics over the operating range parameter description cy7c006a cy7c007a cy7c016a cy7c017a unit ?12 [9] ?15 ?20 min typ max min typ max min typ max v oh output high voltage (v cc = min, i oh = ?4.0 ma) 2.4 ? ? 2.4 ? ? 2.4 ? ? v v ol output low voltage (v cc = min, i oh = +4.0 ma) ? 0.4 ? 0.4 ? 0.4 v v ih input high voltage 2.2 ? 2.2 ? 2.2 ? v v il input low voltage ? 0.8 ? 0.8 ? 0.8 v i oz output leakage current ?10 10 ?10 10 ?10 10 ? a i cc operating current (v cc = max, i out = 0 ma) outputs disabled commercial ? 195 325 ? 190 280 ? 180 275 ma industrial ? 215 305 ? ma i sb1 standby current (both ports ttl level) ce l & ce r ? v ih , f = f max commercial 55 75 50 70 45 65 ma industrial ? 65 95 ? ma i sb2 standby current (one port ttl level) ce l | ce r ? v ih , f = f max commercial 125 205 120 180 110 160 ma industrial ? 135 205 ? ma i sb3 standby current (both ports cmos level) ce l & ce r ? v cc ?? 0.2 v, f = 0 commercial 0.05 0.5 0.05 0.5 0.05 0.5 ma industrial ? 0.05 0.5 ? ma i sb4 standby current (one port cmos level) ce l | ce r ? v ih , f = f max [10, 11] commercial 115 185 110 160 100 140 ma industrial ? 125 175 ? ma notes 8. the voltage on any input or i/o pin cann ot exceed the power pin during power-up. 9. see page 7 for load conditions. 10. pulse width < 20 ns. 11. f max = 1/t rc = all inputs cycling at f = 1/t rc (except output enable). f = 0 means no address or control lines change. this applies only to inputs at cmos level standby i sb3 . [+] feedback
cy7c006a/cy7c007a cy7c016a/cy7c017a document number: 38-06045 rev. *f page 8 of 22 capacitance table [12] parameter description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 5.0 v 10 pf c out output capacitance 10 pf ac test loads and waveforms ac test loads (applicable to ?12 only) [13] (a) normal load (load 1) r1 = 893 ? 5 v output r2 = 347 ? c= 30 pf v th = 1.4 v output c= 30 pf (b) thvenin equivalent (load 1) (c) three-state delay (load 2) r1 = 893 ? r2 = 347 ? 5 v output c= 5pf r th = 250 ? (used for t lz , t hz , t hzwe , & t lzwe including scope and jig) v th = 1.4 v output c (a) load 1 (-12 only) r = 50 ? z 0 = 50 ? 3.0 v gnd 90% 90% 10% 3ns 3 ns 10% all input pulses ? ? 0.00 0.1 0 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 10 15 20 25 30 35 (b) load derating curve capacitance (pf) ?? (ns) for all -12 access times notes 12. tested initially and after any design or proces s changes that may affect these parameters. 13. test conditions: c = 10 pf. [+] feedback
cy7c006a/cy7c007a cy7c016a/cy7c017a document number: 38-06045 rev. *f page 9 of 22 switching characteristics over the operating range [14] parameter description cy7c006a cy7c007a cy7c016a cy7c017a unit ?12 [15] ?15 ?20 min max min max min max read cycle t rc read cycle time 12 ? 15 ? 20 ? ns t aa address to data valid ? 12 ? 15 ? 20 ns t oha output hold from address change 3 ? 3 ? 3 ? ns t ace [16] ce low to data valid ? 12 ? 15 ? 20 ns t doe oe low to data valid ? 8 ? 10 ? 12 ns t lzoe [17, 18, 19] oe low to low z 3 ? 3 ? 3 ? ns t hzoe [17, 18, 19] oe high to high z ? 10 ? 10 ? 12 ns t lzce [17, 18, 19] ce low to low z 3 ? 3 ? 3 ? ns t hzce [17, 18, 19] ce high to high z ? 10 ? 10 ? 12 ns t pu [19] ce low to power-up 0 ? 0 ? 0 ? ns t pd [19] ce high to power-down ? 12 ? 15 ? 20 ns write cycle t wc write cycle time 12 ? 15 ? 20 ? ns t sce [16] ce low to write end 10 ? 12 ? 15 ? ns t aw address valid to write end 10 ? 12 ? 15 ? ns t ha address hold from write end 0 ? 0 ? 0 ? ns t sa [16] address set-up to write start 0 ? 0 ? 0 ? ns t pwe write pulse width 10 ? 12 ? 15 ? ns t sd data set-up to write end 10 ? 10 ? 15 ? ns t hd [22] data hold from write end 0 ? 0 ? 0 ? ns t hzwe [18, 19] r/w low to high z ? 10 ? 10 ? 12 ns t lzwe [18, 19] r/w high to low z 3 ? 3 ? 3 ? ns t wdd [20] write pulse to data delay ? 25 ? 30 ? 45 ns t ddd [20] write data valid to read data valid ? 20 ? 25 ? 30 ns busy timing [21] t bla busy low from address match ? 12 ? 15 ? 20 ns t bha busy high from address mismatch ? 12 ? 15 ? 20 ns notes: 14. test conditions assume signal transition time of 3 ns or less , timing reference levels of 1.5 v, input pulse levels of 0 to 3.0 v, and output loading of the specified i oi /i oh and 30-pf load capacitance. 15. see page 7 for load conditions. 16. to access ram, ce = l, sem = h. to access semaphore, ce = h and sem = l. either condition must be valid for the entire t sce time. 17. at any given temperature and voltag e condition for any given device, t hzce is less than t lzce and t hzoe is less than t lzoe . 18. test conditions used are load 3. 19. this parameter is guaranteed but not tested. 20. for information on port-to-port delay through ram cells from writing port to reading port, refer to read timing with busy wa veform. 21. test conditions used are load 2. 22. for 15 ns industrial parts t hd min. is 0.5 ns. [+] feedback
cy7c006a/cy7c007a cy7c016a/cy7c017a document number: 38-06045 rev. *f page 10 of 22 data retention mode the cy7c006a, cy7c007a, cy7c016a, and cy7c017a are designed with battery backup in mind. data retention voltage and supply current are guaranteed ov er temperature. the following rules ensure data retention: 1. chip enable (ce ) must be held high during data retention, within v cc to v cc ? 0.2 v. 2. ce must be kept between v cc ? 0.2 v and 70% of v cc during the power-up and power-down transitions. 3. the ram can begin operation >t rc after v cc reaches the minimum operating voltage (4.5 v). t blc busy low from ce low 12 15 20 ns t bhc busy high from ce high 12 15 17 ns t ps port set-up for priority 5 5 5 ns t wb r/w high after busy (slave) 0 0 0 ns t wh r/w high after busy high (slave) 11 13 15 ns t bdd [23] busy high to data valid 12 15 20 ns interrupt timing [24] t ins int set time 12 15 20 ns t inr int reset time 12 15 20 ns semaphore timing t sop sem flag update pulse (oe or sem )10 10 10 ns t swrd sem flag write to read time 5 5 5 ns t sps sem flag contention window 5 5 5 ns t saa sem address access time 12 15 20 ns switching characteristics over the operating range [14] (continued) parameter description cy7c006a cy7c007a cy7c016a cy7c017a unit ?12 [15] ?15 ?20 min max min max min max timing parameter test conditions [25] max unit icc dr1 @ vcc dr = 2 v 1.5 ma data retention mode 4.5v 4.5v v cc ? ? 2.0v v cc to v cc ? 0.2v v cc ce t rc v ih notes: 23. t bdd is a calculated parameter and is the greater of t wdd ?t pwe (actual) or t ddd ?t sd (actual). 24. test conditions used are load 2. 25. ce = v cc , v in = gnd to v cc , t a = 25c. this parameter is guaranteed but not tested. [+] feedback
cy7c006a/cy7c007a cy7c016a/cy7c017a document number: 38-06045 rev. *f page 11 of 22 switching waveforms read cycle no. 1 (either port address access) [26, 27, 28] read cycle no. 2 (either port ce /oe access) [26, 29, 30] read cycle no. 3 (either port) [26, 28, 29, 30] notes 26. r/w is high for read cycles. 27. device is continuously selected ce = v il . this waveform cannot be used for semaphore reads. 28. oe = v il . 29. address valid prior to or coincident with ce transition low. 30. to access ram, ce = v il , sem = v ih . to access semaphore, ce = v ih , sem = v il . t rc t aa t oha data valid previous data valid data out address t oha t ace t lzoe t doe t hzoe t hzce data valid t lzce t pu t pd i sb i cc data out oe ce current data out t rc address t aa t oha ce t lzce t abe t hzce t ace t lzce [+] feedback
cy7c006a/cy7c007a cy7c016a/cy7c017a document number: 38-06045 rev. *f page 12 of 22 write cycle no. 1: r/w controlled timing [31, 32, 33, 34] write cycle no. 2: ce controlled timing [31, 32, 33, 38] notes 31. r/w or ce must be high during all address transitions. 32. a write occurs during the overlap (t sce or t pwe ) of a low ce or sem . 33. t ha is measured from the earlier of ce or r/w or (sem or r/w ) going high at the end of write cycle. 34. if oe is low during a r/w controlled write cycle, the write pulse width must be the larger of t pwe or (t hzwe + t sd ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t sd . if oe is high during an r/w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t pwe . 35. to access ram, ce = v il , sem = v ih . 36. transition is measured 500 mv from steady state with a 5-pf l oad (including scope and jig). this parameter is sampled and n ot 100% tested. 37. during this period, the i/o pins are in the out put state, and input signals must not be applied. 38. if the ce or sem low transition occurs simultaneously with or after the r/w low transition, the outputs remain in the high-impedance state. switching waveforms (continued) t aw t wc t pwe t hd t sd t ha ce r/w oe data out data in address t hzoe t sa t hzwe t lzwe [36] [36] [34] [35] note 37 note 37 t aw t wc t sce t hd t sd t ha ce r/w data in address t sa [35] [+] feedback
cy7c006a/cy7c007a cy7c016a/cy7c017a document number: 38-06045 rev. *f page 13 of 22 semaphore read after write timing, either side [39] timing diagram of semaphore contention [40, 41, 42] notes 39. ce = high for the duration of the above timing (both write and read cycle). 40. i/o 0r = i/o 0l = low (request semaphore); ce r = ce l = high. 41. semaphores are reset (available to both ports) at cycle start. 42. if t sps is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpr edictable. switching waveforms (continued) t sop t aa valid adress valid adress t hd data in valid data out valid t oha t aw t ha t ace t sop t sce t sd t sa t pwe t swrd t doe write cycle read cycle oe r/w i/o 0 sem a 0 ?a 2 match t sps a 0l ?a 2l match r/w l sem l a 0r ?a 2r r/w r sem r [+] feedback
cy7c006a/cy7c007a cy7c016a/cy7c017a document number: 38-06045 rev. *f page 14 of 22 timing diagram of read with busy (m/s =high) [43] write timing with busy input (m/s =low) note 43. ce l = ce r = low. switching waveforms (continued) valid t ddd t wdd match match r/w r data in r data outl t wc address r t pwe valid t sd t hd address l t ps t bla t bha t bdd busy l t pwe r/w busy t wb t wh [+] feedback
cy7c006a/cy7c007a cy7c016a/cy7c017a document number: 38-06045 rev. *f page 15 of 22 busy timing diagram no. 1 (ce arbitration) [44] busy timing diagram no. 2 (address arbitration) [44] note 44. if t ps is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side busy will be asserted. switching waveforms (continued) address match t ps t blc t bhc address match t ps t blc t bhc ce r valid first: address l,r busy r ce l ce r busy l ce r ce l address l,r ce l valid first: address match t ps address l busy r address mismatch t rc or t wc t bla t bha address r address match address mismatch t ps address l busy l t rc or t wc t bla t bha address r right address valid first: left address valid first: [+] feedback
cy7c006a/cy7c007a cy7c016a/cy7c017a document number: 38-06045 rev. *f page 16 of 22 interrupt timi ng diagrams notes 45. t ha depends on which enable pin (ce l or r/w l ) is deasserted first. 46. t ins or t inr depends on which enable pin (ce l or r/w l ) is asserted last. switching waveforms (continued) write 7fff t wc t ha read 7fff t rc t inr write 7ffe t wc read 7ffe t inr t rc address r ce l r/w l int l oe l address r r/w r ce r int l address r ce r r/w r int r oe r address l r/w l ce l int r t ins t ha t ins [45] [46] [46] [46] [45] [46] left side sets int r : right side clears int r : right side sets int l : left side clears int l : [+] feedback
cy7c006a/cy7c007a cy7c016a/cy7c017a document number: 38-06045 rev. *f page 17 of 22 table 1. non-contending read/write inputs outputs ce r/w oe sem i/o 0 ? i/o 8 operation h x x h high z deselected: power-down h h l l data out read data in semaphore flag x x h x high z i/o lines disabled h x l data in write into semaphore flag l h l h data out read llx hdata in write l x x l not allowed table 2. interrupt operation example (assumes busy l =busy r =high) left port right port function r/w l ce l oe l a 0 l ?14 l int l r/w r ce r oe r a 0r?14r int r set right int r flag l l x 7fff x x x x x l [48] reset right int r flag x x x x x x l l 7fff h [47] set left int l flag xxx x l [47] llx 7ffe x reset left int l flag x l l 7ffe h [48] xxx x x table 3. semaphore operation example function i/o 0 ? i/o 8 left i/o 0 ? i/o 8 right status no action 1 1 semaphore free left port writes 0 to semaphore 0 1 left port has semaphore token right port writes 0 to semaphore 0 1 no change. right side has no write access to semaphore left port writes 1 to semaphore 1 0 right port obtains semaphore token left port writes 0 to semaphore 1 0 no change. left port has no write access to semaphore right port writes 1 to semaphore 0 1 left port obtains semaphore token left port writes 1 to semaphore 1 1 semaphore free right port writes 0 to semaphore 1 0 right port has semaphore token right port writes 1 to semaphore 1 1 semaphore free left port writes 0 to semaphore 0 1 left port has semaphore token left port writes 1 to semaphore 1 1 semaphore free notes 47. if busy r = l, then no change. 48. if busy l = l, then no change. [+] feedback
cy7c006a/cy7c007a cy7c016a/cy7c017a document number: 38-06045 rev. *f page 18 of 22 ordering information 16k x 8 asynchronous dual-port sram speed (ns) ordering code package name package type operating range 20 cy7c006a-20ac a65 64-pin thin quad flat pack commercial cy7c006a-20axc a65 64-pin pb-free thin quad flat pack commercial cy7c006a-20axi a65 64-pin pb-free thin quad flat pack industrial CY7C006A-20JXC j81 68-pin pb-free plastic leaded chip carrier commercial ordering code definitions temperature range: x = c or i c = commercial; i = industrial x = pb-free (rohs compliant) package type: x = a or j a = 64-pin tqfp j = 68-pin plcc speed grade: 20 ns 06a = depth: 16k 0 = width: 8 7c = dual port sram cy = cypress device 7c cy 0 06a - 20 x x x [+] feedback
cy7c006a/cy7c007a cy7c016a/cy7c017a document number: 38-06045 rev. *f page 19 of 22 package diagrams 64-lead thin plastic quad flat pack (14 x 14 x 1.4 mm) a65 64-lead pb-free thin plastic quad flat pack (14 x 14 x 1.4 mm) a65 51-85046 *d [+] feedback
cy7c006a/cy7c007a cy7c016a/cy7c017a document number: 38-06045 rev. *f page 20 of 22 package diagrams (continued) 80-pin pb-free thin plastic quad flat pack a80 80-pin thin plastic quad flat pack a80 51-85065 *c 68-lead plastic leaded chip carrier j81 68-lead pb-free plastic leaded chip carrier j81 51-85005 *b [+] feedback
cy7c006a/cy7c007a cy7c016a/cy7c017a document number: 38-06045 rev. *f page 21 of 22 document history page document title: cy7c006a/cy7c007a/cy7c016a/cy7c017a 32k/16k x 8, 16k x 9 dual-port static ram document number: 38-06045 rev. ecn no. issue date orig. of change description of change ** 110197 09/29/01 szv change from sp ec number: 38-00831 to 38-06045 *a 122295 12/27/02 rbi power up requirements added to maximum ratings information *b 237620 see ecn ydt removed cross info rmation from features section *c 345376 see ecn aeq removed i-temp versions for both packages, since they are not valid part numbers. *d 387333 see ecn pcx included pb-free logo included package: cy7c006a-20ai included pb-free packages: cy7c006a-15axc, cy7c006a-20axc, cy7c006a-20axi, CY7C006A-20JXC, cy7c007a-20jxc, cy7c016a-15axc *e 2896210 03/22/2010 rame updated ordering information updated package diagram *f 3110296 12/14/2010 eyb updated ordering information . added ordering code definitions . minor edits and updated in new template. [+] feedback
document number: 38-06045 rev. *f revised december 17, 2010 page 22 of 22 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c006a/cy7c007a cy7c016a/cy7c017a ? cypress semiconductor corporation, 2001-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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